1. Field of the Invention
The present invention relates to charge-transfer-device binary or multi-level memory storage structures, and more particularly to an improved memory structure of the type known as serial-parallel-serial (SPS).
2. Description of the Prior Art
Storage structures employing charge-transfer-device technology are well known, as well as the specific example of the serial-parallel-serial (SPS) binary storage memory block. In the text CHARGE TRANSFER DEVICES by Carlo H. Sequin and Michael F. Tompsett, copyright 1975 by Academic Press, Inc. at pages 243-247, a description is given for a coventional binary serial-parallel-serial (SPS) memory block embodied in charge-coupled-device technology. The system described therein consists of a memory block having an input means at the upper left side of the block and an output means at the lower right side of the block. This arrangement is in logical accordance with the usual sequencing and transfer of the stored charge packets, that is, "first in-first out", but suffers the disadvantage that in order to minimize error the output information must be transferred by some independent means back to the input for the comparison necessary for analog to digital conversion using the same digital-to-analog converter.